A. Field of the Invention
The present invention relates to a method for manufacturing a silicon carbide semiconductor device and the silicon carbide semiconductor device. Specifically, the invention relates to a method for manufacturing a silicon carbide semiconductor device having a trench structure and the silicon carbide semiconductor device having a trench structure.
B. Description of the Related Art
In the semiconductor devices such as a metal oxide semiconductor field effect transistor (hereinafter referred to as a “MOSFET”) and an insulated gate bipolar transistor (hereinafter referred to as an “IGBT”) having a trench structure, straight trenches, for example, are formed in a stripe pattern from the surface of a semiconductor substrate.
In the semiconductor devices having a straight trench structure, electric field localization occurs at the end portion of the trench, when a high voltage is applied to the semiconductor devices. When a pointing trench end portion is caused by dry etching, electric field localization is liable to be caused at the pointing trench end portion. As the electric field localizes to the trench end portion and exceeds the breakdown voltage of the semiconductor device to the higher side, there is a high probability that the semiconductor device will break down.
FIG. 43 is an electron micrograph that shows the result of a leakage analysis conducted on a MOSFET having a conventional trench structure. The MOSFET is observed by emission microscopy (hereinafter referred to as “EMS”). In the MOSFET shown in FIG. 43, straight trench 101 is disposed in a silicon carbide semiconductor device (hereinafter referred to sometimes as an “SiC semiconductor device”) that employs a silicon carbide semiconductor substrate (hereinafter referred to as an “SiC substrate”). In end portion 102 (indicated by a double-dotted-chain circle) of trench 101, a light emission caused by current leakage is observed. In the portion that emits light as shown in FIG. 43, electric field localization is liable to result and, therefore, the portion that emits light as shown in FIG. 43 will break down with a high probability.
To avoid the problem described above, the trench end portion is rounded or the trench end portions are connected to each other to remove trench end portions in the silicon semiconductor device (hereinafter referred to as the “Si device”) that employs a silicon (Si) semiconductor substrate.
A semiconductor device as described below that has a trench structure, in which the trench end corner section is rounded, is proposed in the following Patent Document 1. In the semiconductor device proposed in Japanese Unexamined Patent Application Publication No. 2003-188379, the width of the trench in the vicinity of the end portion thereof is set to be narrower in the planar shape than the width of the trench in the trunk portion thereof. The trench is formed by dry-etching such that the depth of the trench in the vicinity of the end portion thereof is set to be shallower than the depth of the trench in the trunk portion thereof and the trench end corner section is rounded. By the structure described above, a singular point is prevented from causing on the gate oxide film or the gate electrode in the trench end corner section to relax the electric field localization to the trench end corner section or to prevent the breakdown voltage in the trench end corner section from decreasing.
The semiconductor device proposed in Japanese Patent Publication No. 4130356 includes a semiconductor layer on a semiconductor substrate; a first cell region and a second cell region in the semiconductor layer, the first cell region and the second cell region being adjacent to each other; each of the first and second cell regions including a plurality of stripe-shaped trench lines extending in perpendicular to the boundary between the first and second cell regions; each of the trench lines having a first end portion and a second end portion; first connection trenches connecting the first end portions of some pairs of the adjacent trench lines such that the first end portions of at least a pair of the adjacent trench lines are not connected to each other; second connection trenches connecting the second end portions of some pairs of the adjacent trench lines such that all the trench lines in each of the first and second cell regions are connected to each other but such that the second end portions of at least another pair of the adjacent trench lines are not connected to each other; gate insulator films in the trench lines, the first connection trenches and the second connection trenches; gate electrodes buried in the trench lines, the first connection trenches and the second connection trenches with the respective gate insulator films interposed therebetween; a gate wiring on the semiconductor layer, the gate wiring being on the boundary between the first and second cell regions, the gate wiring being connected electrically to the gate electrodes; a first electrode on the first major surface of the semiconductor layer; a second electrode on the second major surface of the semiconductor layer; and at least one of the first connection trenches in the second cell region not facing to any of the second connection trenches in the first cell region.
The semiconductor device proposed in Japanese Unexamined Patent Application Publication No. 2001-168329 has a trench structure in which adjacent trenches are connected with each other with a U-shaped connecting trench such that the end portion of a trench facing the chip edge and the end portion of the adjacent trench are connected with each other with the connecting trench having a large curvature and disposed in a p-type well region.
Another semiconductor device proposed in Japanese Unexamined Patent Application Publication No. 2001-332727 has a trench structure, in which adjacent trenches are connected with each other with a U-shaped connecting trench such that the end portion of a trench facing to the chip edge and the end portion of the adjacent trench are connected with each other by the connecting trench, the width thereof is larger than the width of the straight section of the trench.
As a result of investigation conducted by the present inventors, it has been found that the following problems will be caused, if the techniques described above are applied to the SiC semiconductor device. In the following, the problems caused are described, for example, in connection with the application of the technique proposed in Japanese Unexamined Patent Application Publication No. 2001-168329 to the SiC semiconductor device.
FIG. 36 is an electron micrograph of a conventional silicon carbide semiconductor device before the heat treatment thereof from the surface side thereof. The SiC semiconductor device is observed under a scanning electron microscope (hereinafter referred to as a “SEM”). (The SiC semiconductor devices are observed also under a SEM in FIGS. 1 through 31 and in FIG. 33.) Trench 111 is formed in the surface portion of the SiC semiconductor device. Trench 111 is formed of adjoining straight trenches (hereinafter referred to collectively as “straight trench section”) 112 and semicircular connecting trench (hereinafter referred to as “connecting trench section”) 113 that connects the end portions of the adjoining trenches constituting straight trench section 112 with each other with a semicircular curve.
In the SiC semiconductor device shown in FIG. 36, trench 111 is formed by dry-etching. In some portions 114 of connecting trench section 113, the trench width is narrowed or an uneven trench side wall occurs. (Hereinafter, these defects will be referred to as “defective trench formations 114 caused by trench etching” or simply as “defective trench formations 114.”) It is estimated that defective trench formations 114 are caused by the variation of the dry-etching speed depending on the crystal plane of the SiC semiconductor device (the crystal plane dependence of the dry-etching speed).
FIG. 37 is an electron micrograph that shows the conventional silicon carbide semiconductor device after the heat treatment thereof from the surface side thereof.
The heat treatment is conducted in an argon (Ar) gas, to which monosilane (SiH4) is added at the flow rate ratio of 0.4%, under the pressure of 80 Torr and at 1700° C. for 60 minutes. The SiC semiconductor device is observed using a focused ion beam (hereinafter referred to as an “FIB”). (The SiC semiconductor devices are observed using an FIB in also FIGS. 38 through 42.) In the conventional SiC semiconductor device shown in FIG. 36 and treated thermally, it is confirmed that defective portion 115 filled occurs in connecting trench section 113. (Hereinafter defective portion 115 will be referred to as “defective trench formation 115.”)
The states of defective trench formation 115 are observed by cutting out the cross sections of the SiC semiconductor device. FIG. 38 is an electron micrograph observing the cross section along the line segment A-A′ of FIG. 37. FIG. 39 is an electron micrograph observing the cross section along the line segment B-B′ of FIG. 37. FIG. 40 is an electron micrograph observing the cross section along the line segment C-C′ of FIG. 37. FIG. 41 is an electron micrograph observing the cross section along the line segment D-D′ of FIG. 37. FIG. 42 is an electron micrograph observing the cross section along the line segment E-E′ of FIG. 37.
A wolfram (W) protector film is deposited on the SiC semiconductor device for protecting the surface thereof in micro-machining a specific micro area with an FIB. FIGS. 38, 40 and 42 show the trench remaining in the SiC semiconductor device. In contrast, the trenches in the SiC semiconductor devices shown in FIGS. 39 and 41 are filled and almost not remaining in the SiC semiconductor devices.
In manufacturing a semiconductor device having a trench structure, a heat treatment is conducted, after forming trenches, at 1500° or higher to improv the shapes of the trenches and to activate the implanted impurity atoms. In the SiC semiconductor device, the heat treatment as described above narrows the trench in a part of the connecting trench section or deforms the trench to be shallow. It is found that the locations in the connecting trench section, at which the deformations such as a narrowed trench and a shallow trench are caused by the heat treatments, and the magnitudes of the deformations are different depending on the curvature of the connecting trench section.
The curvature of the connecting trench section is determined by the spacing (cell pitch) between the trenches in the straight trench section. In other words, it is found that different magnitudes of unevenness are caused at different locations on the side wall and the bottom plane of the connecting trench section depending on the cell pitch. If the portion of the connecting trench section narrowed by trench-etching (cf. FIG. 36) is further narrowed by a heat treatment, a part of the connecting trench section will be filled. If a part of the connecting trench section is deformed greatly by the unevenness caused by the heat treatment, the unevenness itself will cause defective trench formation.
If the straight trench section is connected with a connecting trench section, a part of the connecting trench section will be filled, as described above, by the heat treatment conducted at 1500° C. or higher on the SiC semiconductor device. If a part of the connecting trench section is filled, an end portion will be caused on the trench or the trench end portion will be pointed. If the electric field localizes to the trench end portion, the SiC semiconductor device will be deteriorated or broken down.
In view of the foregoing, it would be desirable to obviate the problems described above. It would be also desirable to provide a method for manufacturing a silicon carbide semiconductor device that facilitates preventing defects from causing during the manufacture thereof. It would be further desirable to provide a non-defective silicon carbide semiconductor device. The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.